The clock input of the first flip flop and both of its inputs will set to 0. When the first negative clock edge is passed, the output of the first flip flop will be 0. Operation: The first flip flop will be toggled, and the output of this flip flop will be changed from 0 to 1. The output of the first flip flop is passed to both the inputs of the next JK flip flop. So, the first flip flop will work as a toggle flip-flop. Below is the diagram of a 2-bit synchronous counter in which the inputs of the first flip flop, i.e., FF-A, are set to 1. The clock signals produced by all the flip flops are the same as each other. In the synchronous counter, the same clock pulse is passed to the clock input of all the flip flops. The synchronous counter is designed to remove this drawback. The drawback of this system is that it creates the counting delay, and the propagation delay also occurs during the counting stage. So, the counters are connected like a chain. In the Asynchronous counter, the present counter's output passes to the input of the next counter. This input will change the output state of the second flip flop. This output will be taken as a negative edge clock by the second flip flop. Operation: The first flip flop will toggle again, and the output of this flip flop will change from 1 to 0.
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